The design process for integrated circuits has evolved from a relatively simple process, where relatively few circuits were initially placed onto a circuit layout, to modern complex integrated circuits, where computer aided design (CAD) tools are used to realize a circuit layout. The use of CAD tools to lay out complex integrated circuits, such as application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs), is commonly referred to as electronic design automation (EDA). The only feasible technique for designing, verifying, and testing modern complex integrated circuits is with the use of programmable computer systems that enable a user to realize normal circuit implementations.
One technique for specifying an integrated circuit design is with a hardware description language (HDL) such as VHDL. A hardware description language (HDL) enables representation of an integrated circuit design at a logical level, and provides a high level design language. An integrated circuit is represented in several different levels, comprising different layers of abstraction. Silicon compilers, comprising synthesis programs, are used to yield a final implementation wherein the programs generate sufficient detail to proceed directly to silicon fabrication.
A compiler generates a netlist of generic primitive cells during the processing of an HDL. A netlist is a list of all the nets, or collection of pins needing to be electrically connected, in a circuit. The netlist consists of a detailed list of interconnections and logic components, and can include primitive cells such as XOR gates, NAND gates, latches and D-flip flops and their associated interconnections.
The silicon compiler first generates a netlist of independent cells, then applies a particular cell library to the resulting generic netlist via a process called mapping. As a consequence, a dependent mapped netlist is generated which uses standard circuits that are available within a cell library and which are available to the computer system.
Silicon compilers and mapping programs are well understood in the art, and are described in numerous patents including U.S. Pat. Nos. 5,406,497 and 5,831,868.
Design for testability (DFT) forms an important part of the logic synthesis process. More particularly, design for testability (DFT) involves the up-front consideration of product testability considerations while designing a circuit. Low-cost/high-volume manufacturing has recently dictated that product testability be considered at the onset of circuit design, otherwise products will be inherently hard to test and will cost time and money to achieve desired levels of quality.
Accordingly, numerous programs are known for aiding in the testability process of logic synthesis. For example, it is known to take a mapped netlist that is generated from a silicon compiler, and interchange specific memory cells and circuitry with special memory cells that enable the application of test vectors to specific logic portions of an integrated circuit. The application of such special memory cells in order to apply test vectors to stimulate the design is referred to as a design-for-testability (DFT) implementation.
A number of techniques are known for generating non-exhaustive sets of test patterns that validate functionality and identify faults within a circuit design. Automatic test pattern generation (ATPG) programs are known in the art for providing a reduced size test set while maximizing fault coverage for the design. However, these techniques require a significant test area when integrating design-for-testability (DFT) features since present ATPGs transform regular flip-flop elements into MUX flip-flops elements during a scan insertion whether or not the topology of the circuit requires such substitution. Therefore, a technique is required which significantly decreases the test area cost that is associated with integrating design-for-testability (DFT) features into a circuit design.